鐃竣ワ申奪肇侫鐃緒申鐃緒申鐃�
鐃出縁申鐃緒申鐃銃わ申鐃緒申廛鐃獣トフワ申鐃緒申鐃緒申
鐃緒申鐃緒申鐃叔は￥申FreeBSD 鐃緒申鐃出縁申鐃緒申鐃銃わ申鐃緒申廛鐃獣トフワ申鐃緒申鐃緒申亡悗鐃緒申鐃緒申鐃緒申鐃緒申鷆，鐃緒申泙鐃緒申鐃�
| 鐃竣ワ申奪肇侫鐃緒申鐃緒申鐃縮� | TARGET_ARCH | 11.x 鐃緒申鐃楯￥申鐃緒申 Tier | 12.x 鐃緒申鐃楯￥申鐃緒申 Tier | Projected 13.x 鐃緒申鐃楯￥申鐃緒申 Tier |
| 64-bit x86 | amd64 | Tier 1 | Tier 1 | Tier 1 |
| 32-bit x86 | i386 | Tier 1 | Tier 1 | Tier 1 |
| PC98 | pc98 | Tier 2 | Tier 4 | Tier 4 |
| 64-bit ARMv8 | aarch64 | Tier 2 | Tier 2 | Tier 2 |
| 32-bit ARMv4/5 | arm | Tier 2 | Tier 2 | Tier 4 |
| 32-bit big-endian ARM | armeb | Tier 2 | Tier 4 | Tier 4 |
| 32-bit ARMv6 | armv6 | Tier 2 | Tier 2 | Tier 2 |
| 32-bit ARMv7 | armv7 | *1 | Tier 2 | Tier 2 |
| 32-bit MIPS soft-float | mips, mipsel | Tier 3 | Tier 2 | Tier 2 |
| 32-bit MIPS hard-float | mipshf, mipselhf | N/A | Tier 2 | Tier 2 |
| 32-bit MIPS n32 | mipsn32 | Tier 3 | Tier 2 | Tier 2 |
| 64-bit MIPS soft-float | mips64, mips64el | Tier 3 | Tier 2 | Tier 2 |
| 64-bit MIPS hard-float | mips64hf, mips64elhf | N/A | Tier 2 | Tier 2 |
| 32-bit PowerPC | powerpc | Tier 2 | Tier 2 | Tier 2 |
| 32-bit PowerPC with SPE | powerpcspe | Tier 2 | Tier 2 | |
| 64-bit PowerPC | powerpc64 | Tier 2 | Tier 2 | Tier 2 |
| 64-bit RISC-V | riscv64, riscv64sf | Tier 3 | Tier 2 | |
| 64-bit SPARCv9 | sparc64 | Tier 2 | Tier 2 | Tier 4 |
鐃緒申鐃緒申
鐃出縁申鐃緒申鐃銃わ申鐃淑わ申鐃竣ワ申奪肇侫鐃緒申鐃緒申鐃�
鐃淑駕申鐃塾プワ申奪肇侫鐃緒申鐃緒申鐃熟￥申鐃重わ申鐃出￥申鐃緒申鐃緒申鐃緒申 FreeBSD 鐃叔ワ申鐃楯￥申鐃夙わ申鐃緒申討鐃緒申泙鐃緒申鐃緒申鐃�
| 鐃竣ワ申奪肇侫鐃緒申鐃緒申鐃縮� | TARGET_ARCH | 鐃叔緒申鐃緒申鐃楯￥申鐃夙バ￥申鐃緒申鐃緒申鐃� |
| Alpha | alpha | 6.4 |
| Intel IA-64 | ia64 | 10.4 |